1. Field of the Invention
The present invention relates to a bus relay device that relays buses of different specifications. More particularly, this invention relates to a bus relay device in which a plurality of requests inputted from a first bus are arbitrated, converted into signals, and outputted to a second bus. This invention also relates to a bus control system which includes the bus relay device.
2. Description of Related Art
Conventionally, there has been used a bus control system for arbitrating the use of a bus to which a plurality of devices are connected, for example, as described in “AMBATM specification, Rev2, 1999, pp. 18-19”. A device which requests for the use of the bus and uses the bus is called a master, and a device which the master accesses through the bus is called a slave.
Lately, bus control systems become more complicated than before because information processing devices and electronic devices having such bus control systems have been more advanced in terms of the high performance and functions. Accordingly, the number of masters connected to a bus tends to increase. When the device making a request and the device receiving the request differ in bus specification, the bus specification has to be converted to be usable.
In particular, when a master connected to a high-speed access bus makes an access to a slave connected to a low speed access bus, the format of a control signal group must be changed according to the bus specification acceptable to the slave. For example, when the master outputs read and write control signal groups in parallel while the slave sequentially receives the control signal groups one by one, it must be determined which one of the read and write control signal groups is prioritized. Moreover, when a plurality of masters are connected to a bus, the priority order of all the control signal groups transmitted from the plurality of masters must be determined.
FIG. 5 shows an example of a conventional bus control system. As shown in FIG. 5, a bus control system 9 includes masters 10a and 10b, a slave 20, and a bus relay device 80. The bus relay device includes an interconnect section 810 and a bridge section 820. In addition, in the bus control system 9 in FIG. 5, a device on the master side is connected to a high speed access bus 40 and a device on the slave side is connected to a low speed access bus 60. In the example shown in FIG. 5, two masters are connected to the bus relay device 80. Here, signals 41a and 41b and signals 42a and 42b, which are outputted from the masters 10a and 10b, respectively, are control signal groups each containing a plurality of signals. For example, the signal group 41a, which is one of the control signals groups, contains information on an address for a reading operation, the burst length during a burst transmission, and the like. The signal group 42a which is outputted from the master 10a contains information on an address for a writing operation, the burst length during the burst transmission, and the like. The signal group 41b which is outputted from the master 10b is the same as the signal group 41a and the signal group 42b which is outputted from the master 10b is the same as the signal group 42a which is outputted from the master 10a. Note that, a flow of data to be read or written is omitted in FIG. 5. Here, FIG. 6 shows specific examples of read and write control signal groups in high speed and low speed buses. The control signal groups outputted from masters 10a and 10b conform to the high speed bus specification and the control signal group received by the slave 20 conforms to the low speed bus specification.
The masters 10a and 10b support the high speed bus specification and are capable of outputting read and write control signal groups in parallel. The slave 20 supports the low speed bus specification and is not capable of processing, in parallel, the read and write control signal groups outputted from the masters 10a and 10b. 
The bus relay device 80 provides a relay connection between the high speed access bus 40 and the low speed access bus 60. The interconnect section 810 includes a routing function and an arbitration function. Specifically, according to the priority order of masters, the interconnect section 810 selects one of read control signal groups and one of write control signal groups outputted from the plurality of masters 10a and 10b. The interconnect section 810 then outputs the selected control signal groups to the bridge section 820. The bridge section 820 selects any one of the read and write control signal groups inputted from the interconnect section 810, and performs bus protocol conversion of the bus specification of the selected one control signal group from the bus specification for the high speed access bus into that for the low speed access bus. The bridge section 820 then outputs the control signal group with the converted bus specification to the slave 20. A possible example of a process carried out in the bus protocol conversion between the high speed bus specification and the low speed bus specification shown, for example, in FIG. 6 is to adjust the number of address bits between the high speed bus specification and the low speed bus specification. The bridge section 820 converts the number of address bits of the received control signal group of the high speed bus specification into that of the low speed bus specification, and outputs the resultant control signal group to the slave 20.
FIG. 5 shows a case where the interconnect section 810 includes two arbiters 811 and 812, and where the bridge section 820 including an arbiter 821. The arbiter 811 receives the read control signal groups 41a and 41b respectively outputted from the masters 10a and 10b, and outputs one read control signal group 41x (any one of the read control signal groups 41a and 41b) according to the priority order of masters. The arbiter 812 receives the write control signal groups 42a and 42b respectively outputted from the masters 10a and 10b, and outputs one write control signal group 42x (any one of the write control signal groups 42a and 42b) according to the priority order of masters. In addition, the arbiter 821 receives the read control signal group 41x and the write control signal group 42x, and outputs a reading or write control signal group 61 according to the priority order of the reading and write control signal groups.
As just described, the conventional bus control system 9 requires two steps of arbitration processes for a plurality of requests outputted from the plurality of masters. More specifically, the interconnect section 810 performs the arbitration process according to the priority order of the plurality of masters in the first step, and the bridge section 820 performs the arbitration process according to the priority order of the read and write control signal groups in the second step. Furthermore, the bridge section 820 performs a conversion process for converting the bus specification.
In the conventional bus control system 9, the interconnect section 810 and the bridge section 820 each have the arbitration function. Meanwhile, the interconnect section 810 and the bridge section 820 were designed by different designers. Accordingly, a large number of man-hours are needed not only for designing the bridge section but also for inspecting the bridge section.